Fast design-space exploration with FPGA clusters

Clusters of FPGAs are a promising environment for prototyping and evaluation of new MPSoC architectures with a large number of parallel cores. The high complexity of both the MPSoC and the FPGA cluster pose many challenges for the designer [1]. Tools like Synopsys Certify can be used to automatically partition designs on systems with a fixed communication infrastructure, still they do not address the problem that minor changes in the design might require a whole rerun of the mapping procedure. For each FPGA the architecture mapping consists of synthesis, place & route, bitstream generation, and finally the FPGA configuration. While the configuration is done within milliseconds, synthesis, place & route, and bitstream generation easily take several hours to complete. Thus, the evaluation of different architectural variants becomes a very time-consuming task. In design-space exploration typically not all parts of the architecture are changed at a time. Based on this idea, we have developed an approach that utilizes concepts of dynamic reconfiguration to speed-up the exploration. In our environment, the evaluated design consists of a number of pre-synthesized and pre-routed modules and communication structures that can be combined to new architecture variants. This results in a very fast setup of the prototyping environment compared to a completely new synthesis. The design-flow relies on a tool supported rather than an automatic approach. This takes into account that the majority of the targeted application scenarios consists of regular structures instead of a single large design that has to be partitioned to multiple FPGAs.